Job Description:
Candidate is responsible for PCIe Controller design, integration and simulation.
He/she needs to debug PCIe-related issue in ASIC or FPGA.
He/she also needs to work with HW and FW team closely for the product development.
Requirement:
Master's degree in electrical or electronics engineering.
At least 7 years(preferred) experiences in RTL design and verification.
Design experience in High Speed IO Controllers like PCIe, or SATA.
Good ability to integrate Phy IP.
Familiar with FPGA and silicon debug.
Good communication skill and team working spirit.