ASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta’s AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, tcl and SystemVerilog.
RESPONSIBILITIES
Perform PPA optimization with Fusion compiler.
Perform RTL and netlist level Power analysis
Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction
Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)
Implement some blocks at RTL and UPF
Ability to document and communicate clearly
MINIMUM QUALIFICATIONS
10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer
Experience with power estimation tools and synthesis, some physical design
Knowledge of power trade-offs in design and back end implementation
Hands-on experience in scripting, data analysis
BS in Electrical Engineering/Computer Science or equivalent experience
Job Types: Full-time, Contract
Benefits:
- 401(k)
- Dental insurance
- Health insurance
- Vision insurance
Experience level:
Schedule:
- 8 hour shift
- Monday to Friday
Work Location: On the road